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Dual IF Receiver AD6642
FEATURES
11-bit, 200 MSPS output data rate per channel Integrated noise shaping requantizer (NSR) Performance with NSR enabled SNR: 75.5 dBFS in 40 MHz band to 70 MHz @ 185 MSPS SNR: 73.7 dBFS in 60 MHz band to 70 MHz @ 185 MSPS Performance with NSR disabled SNR: 66.5 dBFS to 70 MHz @ 185 MSPS SFDR: 83 dBc to 70 MHz @ 185 MSPS Low power: 0.62 W @ 185 MSPS 1.8 V analog supply operation 1.8 V LVDS (ANSI-644 levels) output 1-to-8 integer clock divider Internal ADC voltage reference 1.75 V p-p analog input range (programmable to 2.0 V p-p) Differential analog inputs with 800 MHz bandwidth 95 dB channel isolation/crosstalk Serial port control User-configurable built-in self-test (BIST) capability Energy-saving power-down modes
FUNCTIONAL BLOCK DIAGRAM
AVDD AGND DRVDD DRGND
AD6642
VIN+A VIN-A VCMA VIN+B VIN-B VCMB REFERENCE CLOCK DIVIDER SERIAL PORT PIPELINE ADC 14 NOISE SHAPING REQUANTIZER 11 PIPELINE ADC 14 NOISE SHAPING REQUANTIZER 11
DATA MULTIPLEXER AND LVDS DRIVERS
DC0AB D0AB
D10AB
MODE SYNC PDWN
08563-001
SCLK
SDIO
CSB
CLK+ CLK-
Figure 1.
PRODUCT HIGHLIGHTS
1. 2. Two ADCs are contained in a small, space-saving, 10 mm x 10 mm x 1.4 mm, 144-ball CSP_BGA package. Pin selectable noise shaping requantizer (NSR) function that allows for improved SNR within a reduced bandwidth of up to 60 MHz at 185 MSPS. LVDS digital output interface configured for low cost FPGA families. 120 mW per ADC core power consumption. Operation from a single 1.8 V supply. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary or twos complement), NSR, power-down, test modes, and voltage reference mode. On-chip integer 1-to-8 input clock divider and multichip sync function to support a wide range of clocking schemes and multichannel subsystems.
APPLICATIONS
Communications Diversity radio and smart antenna (MIMO) systems Multimode digital receivers (3G) WCDMA, LTE, CDMA2000 WiMAX, TD-SCDMA I/Q demodulation systems General-purpose software radios
3. 4. 5. 6.
7.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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AD6642 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications..................................................................................... 4 DC Specifications ......................................................................... 4 AC Specifications.......................................................................... 5 Digital Specifications ................................................................... 6 Switching Specifications .............................................................. 7 Timing Specifications .................................................................. 8 Absolute Maximum Ratings............................................................ 9 Thermal Characteristics .............................................................. 9 ESD Caution .................................................................................. 9 Pin Configuration and Function Descriptions ........................... 10 Typical Performance Characteristics ........................................... 12 Equivalent Circuits ......................................................................... 15 Theory of Operation ...................................................................... 16 ADC Architecture ...................................................................... 16 Analog Input Considerations.................................................... 16 Clock Input Considerations ...................................................... 18 Power Dissipation and Standby Mode .................................... 20 Channel/Chip Synchronization ................................................ 20 Digital Outputs ........................................................................... 21 Timing ......................................................................................... 21 Noise Shaping Requantizer (NSR) ............................................... 22 22% BW Mode (>40 MHz @ 184.32 MSPS) ........................... 22 33% BW Mode (>60 MHz @ 184.32 MSPS) ........................... 22 MODE Pin ................................................................................... 23 Built-In Self-Test (BIST) and Output Test .................................. 24 Built-In Self-Test (BIST) ............................................................ 24 Output Test Modes ..................................................................... 24 Serial Port Interface (SPI) .............................................................. 25 Configuration Using the SPI ..................................................... 25 Hardware Interface..................................................................... 25 Memory Map .................................................................................. 26 Reading the Memory Map Register Table............................... 26 Memory Map Register Table ..................................................... 27 Memory Map Register Descriptions ........................................ 29 Applications Information .............................................................. 30 Design Guidelines ...................................................................... 30 Outline Dimensions ....................................................................... 31 Ordering Guide .......................................................................... 31
REVISION HISTORY
10/09--Revision 0: Initial Version
Rev. 0 | Page 2 of 32
AD6642 GENERAL DESCRIPTION
The AD6642 is an 11-bit, 200 MSPS, dual-channel intermediate frequency (IF) receiver specifically designed to support multiantenna systems in telecommunication applications where high dynamic range performance, low power, and small size are desired. The device consists of two high performance analog-to-digital converters (ADCs) and noise shaping requantizer (NSR) digital blocks. Each ADC consists of a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features a wide bandwidth switched-capacitor sampling network within the first stage of the differential pipeline. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) compensates for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows for improved SNR performance in a smaller frequency band within the Nyquist bandwidth. The device supports two different output modes selectable via the external MODE pin or the SPI. With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6642 supports enhanced SNR performance within a limited portion of the Nyquist bandwidth while maintaining an 11-bit output resolution. The NSR block can be programmed to provide a bandwidth of either 22% or 33% of the sample clock. For example, with a sample clock rate of 185 MSPS, the AD6642 can achieve up to 75.5 dBFS SNR for a 40 MHz bandwidth in the 22% mode and up to 73.7 dBFS SNR for a 60 MHz bandwidth in the 33% mode. With the NSR block disabled, the ADC data is provided directly to the output with a resolution of 11 bits. The AD6642 can achieve up to 66.5 dBFS SNR for the entire Nyquist bandwidth when operated in this mode. This allows the AD6642 to be used in telecommunication applications such as a digital predistortion observation path where wider bandwidths are desired. After digital signal processing, multiplexed output data is routed into two 11-bit output ports such that the maximum data rate is 400 Mbps (DDR). These outputs are set at 1.8 V LVDS and support ANSI-644 levels. The AD6642 receiver digitizes a wide spectrum of IF frequencies. Each receiver is designed for simultaneous reception of a separate antenna. This IF sampling architecture greatly reduces component cost and complexity compared with traditional analog techniques or less integrated digital methods. Flexible power-down options allow significant power savings. Programming for device setup and control is accomplished using a 3-wire SPI-compatible serial interface with numerous modes to support board-level system testing. The AD6642 is available in a Pb-free/RoHS compliant, 144-ball, 10 mm x 10 mm chip scale package ball grid array (CSP_BGA) and is specified over the industrial temperature range of -40C to +85C.
Rev. 0 | Page 3 of 32
AD6642 SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = -1.0 dBFS differential input, and default SPI, unless otherwise noted. Table 1.
Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) 1 Integral Nonlinearity (INL)1 MATCHING CHARACTERISTIC Offset Error Gain Error TEMPERATURE DRIFT Offset Error Gain Error ANALOG INPUT Input Range Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance 2 POWER SUPPLIES Supply Voltage AVDD DRVDD Supply Current IAVDD1 IDRVDD1 (1.8 V LVDS) POWER CONSUMPTION Sine Wave Input1 Standby Power 3 Power-Down Power
1 2 3
Temperature Full Full Full Full Full Full Full Full Full Full Full Full Full Full
Min 11
Typ
Max
Unit Bits
-4.5
Guaranteed 2 3 0.1 0.2 2.5 1 2 40
7.4 7 0.5 0.5 8.3 3
mV % FSR LSB LSB mV % FSR ppm/C ppm/C
-2.4
1.4
1.75 0.9 20 5
2.0
V p-p V k pF
Full Full Full Full Full Full Full
1.7 1.7
1.8 1.8 265 79 619 83 4.5
1.9 1.9 291 89 684 18
V V mA mA mW mW mW
Measured with a 10 MHz, 0 dBFS sine wave, with 100 termination on each LVDS output pair. Input capacitance refers to the effective capacitance between one differential input pin and AGND. Standby power is measured with a dc input and the CLKx pins inactive (set to AVDD or AGND).
Rev. 0 | Page 4 of 32
AD6642
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = -1.0 dBFS differential input, and default SPI, unless otherwise noted. Table 2.
Parameter 1 SIGNAL-TO-NOISE-RATIO (SNR)--NSR DISABLED fIN = 30 MHz fIN = 70 MHz fIN = 170 MHz fIN = 250 MHz SIGNAL-TO-NOISE-RATIO (SNR)--NSR ENABLED 22% BW Mode fIN = 70 MHz fIN = 170 MHz fIN = 230 MHz 33% BW Mode fIN = 70 MHz fIN = 170 MHz fIN = 230 MHz SIGNAL-TO-NOISE-AND DISTORTION (SINAD) fIN = 30 MHz fIN = 70 MHz fIN = 170 MHz fIN = 250 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 30 MHz fIN = 70 MHz fIN = 170 MHz fIN = 250 MHz WORST SECOND OR THIRD HARMONIC fIN = 30 MHz fIN = 70 MHz fIN = 170 MHz fIN = 250 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 30 MHz fIN = 70 MHz fIN = 170 MHz fIN = 250 MHz WORST OTHER HARMONIC (FOURTH THROUGH EIGHTH) fIN = 30 MHz fIN = 70 MHz fIN = 170 MHz fIN = 250 MHz TWO-TONE SFDR (-7 dBFS) fIN1 = 169 MHz, fIN2 = 172 MHz CROSSTALK 2 ANALOG INPUT BANDWIDTH
1 2
Temperature 25C 25C Full 25C
Min
Typ 66.5 66.5 66.1 65.5
Max
Unit dBFS dBFS dBFS dBFS
65.7
25C Full 25C 25C Full 25C 25C 25C Full 25C 25C 25C Full 25C 25C 25C Full 25C 25C 25C Full 25C 25C 25C Full 25C 25C Full 25C
72.8
75.5 74.4 72.8 73.7 72.6 71.0 65.5 66.3 65.6 64.3 10.6 10.7 10.6 10.3 -90 -83 -78 -80 90 83 78 80 -100 -96 -90 -95 82 95 800
dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS Bits Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dB MHz
71.0
64.1
10.3
-72
72
-82
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. Crosstalk is measured at 155 MHz with -1 dBFS on one channel and no input on the alternate channel.
Rev. 0 | Page 5 of 32
AD6642
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = -1.0 dBFS differential input, and default SPI, unless otherwise noted. Table 3.
Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK-) Logic Compliance Internal Common-Mode Bias Differential Input Voltage Input Voltage Range High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance SYNC INPUT Logic Compliance Internal Bias Input Voltage Range High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUT (CSB) 1 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUT (SCLK) 2 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUT/OUTPUT (SDIO)2 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUT (MODE)1 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Temperature Min Typ CMOS/LVDS/LVPECL 0.9 0.2 AGND - 0.3 1.2 0 -10 -10 8 3.6 AVDD + 0.2 2.0 0.8 +10 +10 12 Max Unit
Full Full Full Full Full Full Full Full Full
10 4 CMOS 0.9
V V p-p V V V A A k pF
Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full
AGND 1.2 AGND -100 -100 12
16 1
AVDD AVDD 0.6 +100 +100 20
V V V V A A k pF V V A A k pF V V A A k pF V V A A k pF V V A A
1.22 0 -10 40 26 2 1.22 0 -92 -10 26 2 1.22 0 -10 38 26 5 1.22 0 -10 40
Rev. 0 | Page 6 of 32
2.1 0.6 +10 132
2.1 0.6 -135 +10
2.1 0.6 +10 128
2.1 0.6 +10 132
AD6642
Parameter Input Resistance Input Capacitance LOGIC INPUT (PDWN)2 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance DIGITAL OUTPUTS (LVDS) Differential Output Voltage (VOD) Output Offset Voltage (VOS)
1 2
Temperature Full Full Full Full Full Full Full Full Full Full
Min
Typ 26 2
Max
Unit k pF V V A A k pF mV V
1.22 0 -90 -10 26 5 247 1.125
2.1 0.6 -134 +10
454 1.375
Pull up. Pull down.
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = -1.0 dBFS differential input, and default SPI, unless otherwise noted. Table 4.
Parameter CLOCK INPUT PARAMETERS Input Clock Rate Conversion Rate 1 CLK Pulse Width High (tCH) Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) DATA OUTPUT PARAMETERS Data Propagation Delay (tPD) DCO Propagation Delay (tDCO) DCO to Data Skew (tSKEW) Pipeline Delay (Latency) With NSR Enabled Wake-Up Time 2 OUT-OF-RANGE RECOVERY TIME
1 2
Temperature Full Full Full Full Full Full Full Full Full Full Full Full
Min
Typ
Max 625 200
Unit MHz MSPS ns ns ps rms ns ns ns Cycles Cycles s Cycles
40
185 2.7 1.3 0.13
4.35 4.55
3.0 3.2 -0.4
-0.2 9 12 1.2 2
5.7 5.9 0
Conversion rate is the clock rate after the divider. Wake-up time is dependent on the value of the decoupling capacitors.
Rev. 0 | Page 7 of 32
AD6642
TIMING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = -1.0 dBFS differential input, and default SPI, unless otherwise noted. Table 5.
Parameter SYNC TIMING REQUIREMENTS tSSYNC tHSYNC SPI TIMING REQUIREMENTS tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO tDIS_SDIO Description SYNC to rising edge of CLK setup time SYNC to rising edge of CLK hold time Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the SCLK Setup time between CSB and SCLK Hold time between CSB and SCLK SCLK pulse width high SCLK pulse width low Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge 2 2 40 2 2 10 10 10 10 Min Typ 0.24 0.40 Max Unit ns ns ns ns ns ns ns ns ns ns ns
Timing Diagrams
N-1 N
tA
N+3
N+4 N+5
VIN
N+1
N+2
tCH
CLK+ CLK- DCO+ DCO-
tCL
1/fS
tDCO
tSKEW tPD
D10+AB (MSB) D10A D10-AB (MSB) D10B D10A D10B D10A D10B D10A D10B D10A D10B D10A D10B D10A D10B
D0A D0-AB (LSB)
D0B
D0A
D0B
D0A
D0B
D0A
D0B
D0A
D0B
D0A
D0B
D0A
D0B
Figure 2. Data Output Timing
CLK+
tSSYNC
SYNC
tHSYNC
08563-003
Figure 3. SYNC Input Timing Requirements
Rev. 0 | Page 8 of 32
08563-002
D0+AB (LSB)
AD6642 ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter AVDD to AGND DRVDD to AGND VIN+x, VIN-x to AGND CLK+, CLK- to AGND SYNC to AGND VCMx to AGND CSB to AGND SCLK to AGND SDIO to AGND PDWN to AGND MODE to AGND Digital Outputs to AGND DCO+AB, DCO-AB to AGND Operating Temperature Range (Ambient) Maximum Junction Temperature Under Bias Storage Temperature Range (Ambient) Rating -0.3 V to +2.0 V -0.3 V to +2.0 V -0.3 V to AVDD + 0.2 V -0.3 V to AVDD + 0.2 V -0.3 V to AVDD + 0.2 V -0.3 V to AVDD + 0.2 V -0.3 V to DRVDD + 0.2 V -0.3 V to DRVDD + 0.2 V -0.3 V to DRVDD + 0.2 V -0.3 V to DRVDD + 0.2 V -0.3 V to DRVDD + 0.2 V -0.3 V to DRVDD + 0.2 V -0.3 V to DRVDD + 0.2 V -40C to +85C 150C -65C to +150C
THERMAL CHARACTERISTICS
The values in Table 7 are per JEDEC JESD51-7 plus JEDEC JESD25-5 for a 2S2P test board. Typical JA is specified for a 4-layer PCB with a solid ground plane. As shown in Table 7, airflow improves heat dissipation, which reduces JA. In addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes reduces JA. Table 7.
Package Type 144-Ball CSP_BGA, 10 mm x 10 mm (BC-144-1)
1 2 3
Airflow Velocity 0 m/s 1 m/s 2.5 m/s
JA1 26.9 24.2 23.0
JC2 8.9
JB3 6.6
Unit C/W
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). Per MIL-STD 883, Method 1012.1. Per JEDEC JESD51-8 (still air).
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
The values in Table 8 are from simulations. The PCB is a JEDEC multilayer board. Thermal performance for actual applications requires careful inspection of the conditions in the application to determine whether they are similar to those assumed in these calculations. Table 8.
Package Type 144-Ball CSP_BGA, 10 mm x 10 mm (BC-144-1) Airflow Velocity 0 m/s 1 m/s 2.5 m/s JB 14.4 14.0 13.9 JT 0.23 0.50 0.53 Unit C/W
ESD CAUTION
Rev. 0 | Page 9 of 32
AD6642 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1 A B C D E F G H J K L M AGND AGND DNC DNC AGND AGND DRGND DRVDD DNC DNC DNC DNC 2 DNC AGND AGND DNC AVDD AGND DRGND DRVDD DNC DNC DNC DNC 3 DNC DNC AGND AGND AVDD AGND DRGND DRVDD DNC DNC DNC DNC 4 AGND AGND CSB AVDD AVDD AGND DRGND DRVDD DNC DNC DNC DNC 5 AVDD AVDD SDIO AVDD AVDD AGND DRGND DRVDD DNC DNC DNC DNC 6 CLK- AVDD SCLK AVDD AVDD AGND DRGND DRVDD DNC DNC DNC DNC 7 CLK+ AVDD PDWN AVDD AVDD AGND DRGND DRVDD D0-AB D0+AB D1-AB D1+AB 8 AVDD AVDD SYNC AVDD AVDD AGND DRGND DRVDD D2-AB D2+AB D3-AB D3+AB 9 AGND AGND MODE AVDD AVDD AGND DRGND DRVDD D4-AB D4+AB D5-AB D5+AB 10 VIN-B VCMB AGND AGND AVDD AGND DRGND DRVDD D6-AB D6+AB D7-AB D7+AB 11 VIN+B AGND AGND VCMA AVDD AGND DRGND DRVDD D8-AB D8+AB D9-AB D9+AB 12 AGND AGND VIN+A VIN-A AGND AGND DRGND DRVDD D10-AB D10+AB DCO-AB DCO+AB
08563-004
Figure 4. Pin Configuration (Top View)
Table 9. Pin Function Descriptions
Pin No. A5, A8, B5, B6, B7, B8, D4, D5, D6, D7, D8, D9, E2, E3, E4, E5, E6, E7, E8, E9, E10, E11 A1, A4, A9, A12, B1, B2, B4, B9, B11, B12, C2, C3, C10, C11, D3, D10, E1, E12, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12 H1, H2, H3, H4, H5, H6, H7, H8, H9, H10, H11, H12 G1, G2, G3, G4, G5, G6, G7, G8, G9, G10, G11, G12 A7 A6 C12 D12 D11 A11 A10 B10 A2, A3, B3, C1, D1, D2, J1 to J6, K1 to K6, L1 to L6, M1 to M6 K7 J7 M7 L7 Mnemonic AVDD Type Supply Description Analog Power Supply (1.8 V Nominal)
AGND
Ground
Analog Ground
DRVDD
Supply
Digital Output Driver Supply (1.8 V Nominal)
DRGND
Ground
Digital Output Driver Ground
CLK+ CLK- VIN+A VIN-A VCMA VIN+B VIN-B VCMB DNC
Input Input Input Input Output Input Input Output
ADC Clock Input--True ADC Clock Input--Complement Differential Analog Input Pin (+) for Channel A Differential Analog Input Pin (-) for Channel A Common-Mode Level Bias Output for Analog Input Channel A Differential Analog Input Pin (+) for Channel B Differential Analog Input Pin (-) for Channel B Common-Mode Level Bias Output for Analog Input Channel B Do Not Connect
D0+AB D0-AB D1+AB D1-AB
Output Output Output Output
Channel A and Channel B LVDS Output Data 0--True Channel A and Channel B LVDS Output Data 0--Complement Channel A and Channel B LVDS Output Data 1--True Channel A and Channel B LVDS Output Data 1--Complement
Rev. 0 | Page 10 of 32
AD6642
Pin No. K8 J8 M8 L8 K9 J9 M9 L9 K10 J10 M10 L10 K11 J11 M11 L11 K12 J12 M12 L12 C9 C8 C7 C6 C5 C4 Mnemonic D2+AB D2-AB D3+AB D3-AB D4+AB D4-AB D5+AB D5-AB D6+AB D6-AB D7+AB D7-AB D8+AB D8-AB D9+AB D9-AB D10+AB D10-AB DCO+AB DCO-AB MODE SYNC PDWN SCLK SDIO CSB Type Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input Input Input Input Input/Output Input Description Channel A and Channel B LVDS Output Data 2--True Channel A and Channel B LVDS Output Data 2--Complement Channel A and Channel B LVDS Output Data 3--True Channel A and Channel B LVDS Output Data 3--Complement Channel A and Channel B LVDS Output Data 4--True Channel A and Channel B LVDS Output Data 4--Complement Channel A and Channel B LVDS Output Data 5--True Channel A and Channel B LVDS Output Data 5--Complement Channel A and Channel B LVDS Output Data 6--True Channel A and Channel B LVDS Output Data 6--Complement Channel A and Channel B LVDS Output Data 7--True Channel A and Channel B LVDS Output Data 7--Complement Channel A and Channel B LVDS Output Data 8--True Channel A and Channel B LVDS Output Data 8--Complement Channel A and Channel B LVDS Output Data 9--True Channel A and Channel B LVDS Output Data 9--Complement Channel A and Channel B LVDS Output Data 10--True Channel A and Channel B LVDS Output Data 10--Complement Data Clock LVDS Output for Channel A and Channel B--True Data Clock LVDS Output for Channel A and Channel B--Complement Mode Select Pin (Logic Low Enables NSR; Logic High Disables NSR) Digital Synchronization Pin Power-Down Input (Active High) SPI Clock SPI Data SPI Chip Select (Active Low)
Rev. 0 | Page 11 of 32
AD6642 TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = 185 MSPS, 1.75 V p-p differential input, VIN = -1.0 dBFS, 32k sample, TA = 25C, unless otherwise noted.
0 0
-20
fS = 185MSPS fIN = 30.3MHz @ -1dBFS
SNR = 65.7dB (66.7dBFS) SFDR = 89.7dBc
AMPLITUDE (dBFS)
-20
fS = 185MSPS fIN = 200.3MHz @ -1dBFS
SNR = 64.8dB (65.8dBFS) SFDR = 80dBc
AMPLITUDE (dBFS)
-40
-40
-60 SECOND HARMONIC
-60
SECOND HARMONIC
-80
THIRD HARMONIC
-80
THIRD HARMONIC
-100
-100
08563-005
0
10
20
30
40 50 60 FREQUENCY (MHz)
70
80
90
0
10
20
30
40 50 60 FREQUENCY (MHz)
70
80
90
Figure 5. Single-Tone FFT with fIN = 30.3 MHz
Figure 8. Single-Tone FFT with fIN = 200.3 MHz
0
0
-20
fS = 185MSPS fIN = 70.3MHz @ -1dBFS
SNR = 65.4dB (66.4dBFS) SFDR = 86dBc
AMPLITUDE (dBFS)
-20
fS = 185MSPS fIN = 230.3MHz @ -1dBFS
SNR = 64.6dB (65.6dBFS) SFDR = 86.1dBc
AMPLITUDE (dBFS)
-40
-40
-60 THIRD HARMONIC -80 SECOND HARMONIC
-60 THIRD HARMONIC SECOND HARMONIC
-80
-100
-100
08563-006
0
10
20
30
40 50 60 FREQUENCY (MHz)
70
80
90
0
10
20
30
40 50 60 FREQUENCY (MHz)
70
80
90
Figure 6. Single-Tone FFT with fIN = 70.3 MHz
Figure 9. Single-Tone FFT with fIN = 230.3 MHz
0
0
-20
fS = 185MSPS fIN = 140.1MHz @ -1dBFS
SNR = 65.3dB (66.3dBFS) SFDR = 88dBc
-20 -40 -60 -80 -100 -120 -140
fS = 185MSPS fIN = 140.1MHz @ -1.6dBFS
NSR 22% BW MODE, TW = 28 SNR = 73dB (74.6dBFS) (IN-BAND) SFDR = 89.7dBc (IN-BAND)
AMPLITUDE (dBFS)
-40
AMPLITUDE (dBFS)
-60 THIRD HARMONIC SECOND HARMONIC
SECOND HARMONIC THIRD HARMONIC
-80
-100
08563-007
0
10
20
30
40 50 60 FREQUENCY (MHz)
70
80
90
0
10
20
30
40 50 60 FREQUENCY (MHz)
70
80
90
Figure 7. Single-Tone FFT with fIN = 140.1 MHz
Figure 10. Single-Tone FFT with fIN = 140.1 MHz, NSR Enabled in 22% BW Mode with Tuning Word = 28
Rev. 0 | Page 12 of 32
08563-110
-120
08563-109
-120
-120
08563-108
-120
-120
AD6642
0 -20 -40 -60 -80 -100 -120 -140 THIRD HARMONIC SECOND HARMONIC fS = 185MSPS fIN = 230.3MHz @ -1.6dBFS
NSR 33% BW MODE, TW = 17 SNR = 69.3dB (71dBFS) (IN-BAND) SFDR = 85.4dBc (IN-BAND)
95 90 85 SFDR (dBc) 80 75 70 SNR (dBFS) 65 60
08563-111
SNR/SFDR (dBFS/dBc)
AMPLITUDE (dBFS)
0
10
20
30
40 50 60 FREQUENCY (MHz)
70
80
90
60
110
160 210 INPUT FREQUENCY (MHz)
260
300
Figure 11. Single-Tone FFT with fIN = 230.3 MHz, NSR Enabled in 33% BW Mode with Tuning Word = 17
Figure 14. Single-Tone SNR/SFDR vs. Input Frequency (fIN) with 2.0 V p-p Full Scale
100 90
95 90 85
SNR/SFDR (dBFS/dBc)
SFDR (dBc)
SNR/SFDR (dBc AND dBFS)
80 70 60 50 40 30 20 10 0 SNR (dBc) SFDR (dBc) SNR (dBFS) SFDR (dBFS)
80 75 70 65 60 55
08563-015 08563-016
SNR (dBFS)
50
-90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0
INPUT AMPLITUDE (dBFS)
08563-112
30
50
70
90
110 130 150 170 190 SAMPLE RATE (MSPS)
210
230
250
Figure 12. Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = 70.3 MHz
Figure 15. Single-Tone SNR/SFDR vs. Sample Rate (fS) with fIN = 70.1 MHz
95 90 85
AMPLITUDE (dBFS)
0
-20
SFDR = 81.8dBc
fS = 185MSPS fIN1 = 169.1MHz @ -7dBFS fIN2 = 172.1MHz @ -7dBFS
SNR/SFDR (dBFS/dBc)
SFDR (dBc) 80 75 70 SNR (dBFS) 65 60 60 110 160 210 INPUT FREQUENCY (MHz) 260 300
-40
-60
-80
-100
08563-013
-120
0
10
20
30
40 50 60 FREQUENCY (MHz)
70
80
90
Figure 13. Single-Tone SNR/SFDR vs. Input Frequency (fIN) with 1.75 V p-p Full Scale
Figure 16. Two-Tone FFT with fIN1 = 169.1 MHz and fIN2 = 172.1 MHz
Rev. 0 | Page 13 of 32
08563-114
AD6642
0
0.20 0.15 0.10
-20
SFDR/IMD3 (dBc AND dBFS)
DNL ERROR (LSB)
-40 IMD3 (dBc) -60
SFDR (dBc)
0.05 0 -0.05 -0.10 -0.15
-80 SFDR (dBFS) -100 IMD3 (dBFS)
08563-017
-78
-66 -54 -42 -30 INPUT AMPLITUDE (dBFS)
-18
-6
0
500
1000 OUTPUT CODE
1500
2000
Figure 17. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 169.1 MHz and fIN2 = 172.1 MHz
Figure 20. DNL with fIN = 30.3 MHz
1,200,000
69 68
1,000,000
67
NUMBER OF HITS
800,000 SNR (dBFS)
66 65 64 63 62
600,000
400,000
200,000
61
08563-018
N-3
N-2
N-1 N N+1 OUTPUT CODE
N+2
N+3
30
35
40
45
50
55
60
65
70
DUTY CYCLE (%)
Figure 18. Grounded Input Histogram
Figure 21. SNR vs. Duty Cycle with fIN = 10.3 MHz
1.0 0.8 0.6
INL ERROR (LSB)
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 0 500 1000 OUTPUT CODE 1500 2000
08563-019
-1.0
Figure 19. INL with fIN = 30.3 MHz
Rev. 0 | Page 14 of 32
08563-021
0
60
08563-020
-120 -90
-0.20
AD6642 EQUIVALENT CIRCUITS
AVDD
SCLK OR PDWN 350 30k
VIN
08563-008
Figure 22. Equivalent Analog Input Circuit
Figure 26. Equivalent SCLK and PDWN Input Circuit
AVDD
AVDD
AVDD 0.9V CLK+ 15k 15k
AVDD
CSB OR MODE
30k
350
CLK-
08563-009
Figure 23. Equivalent Clock Input Circuit
Figure 27. Equivalent CSB and MODE Input Circuit
DRVDD
DRVDD
V+ DATAOUT- V-
V- DATAOUT+ V+
08563-010
SDIO
350 30k
Figure 24. Equivalent LVDS Output Circuit
Figure 28. Equivalent SDIO Circuit
AVDD
AVDD
SYNC 16k 0.9V
0.9V
Figure 25. Equivalent SYNC Input Circuit
08563-025
Rev. 0 | Page 15 of 32
08563-011
08563-014
08563-012
AD6642 THEORY OF OPERATION
ADC ARCHITECTURE
The AD6642 architecture consists of a dual front-end sampleand-hold circuit, followed by a pipelined, switched-capacitor ADC. The quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. Alternately, the 14-bit result can be processed through the noise shaping requantizer (NSR) block before it is sent to the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on the preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor digitalto-analog converter (DAC) and an interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The input stage of each channel contains a differential sampling circuit that can be ac- or dc-coupled in differential or singleended modes. The output staging block aligns the data, corrects errors, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output drive current. During power-down, the output buffers go into a high impedance state. The AD6642 dual IF receiver can simultaneously digitize two channels, making it ideal for diversity reception and digital predistortion (DPD) observation paths in telecommunication systems. Synchronization capability is provided to allow synchronized timing between multiple channels or multiple devices. Programming and control of the AD6642 are accomplished using a 3-wire SPI-compatible serial interface. A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. A shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network creates a low-pass filter at the ADC input; therefore, the precise values are dependent on the application. In intermediate frequency (IF) undersampling applications, any shunt capacitors should be reduced. In combination with the driving source impedance, the shunt capacitors limit the input bandwidth. For more information on this subject, see Application Note AN-742, Frequency Domain Response of Switched-Capacitor ADCs; Application Note AN-827, A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs; and the Analog Dialogue article, "Transformer-Coupled Front-End for Wideband A/D Converters" (see www.analog.com).
BIAS S CS VIN+ CPAR1 CPAR2 H CS VIN- CPAR1 S
08563-037
S CFB
S
S
CPAR2 BIAS
S
CFB
Figure 29. Switched-Capacitor Input
For best dynamic performance, the source impedances driving the VIN+ and VIN- pins should be matched. An internal differential reference buffer creates positive and negative reference voltages that define the input span of the ADC core. The span of the ADC core is set by this buffer to 2 x VREF.
Input Common Mode
The analog inputs of the AD6642 are not internally dc biased. In ac-coupled applications, the user must provide this bias externally. An on-board common-mode voltage reference is included in the design and is available from the VCMx pins. Optimum performance is achieved when the common-mode voltage of the analog input is set by the VCMx pin voltage (typically 0.5 x AVDD). The VCMx pins must be decoupled to ground by a 0.1 F capacitor.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD6642 is a differential switchedcapacitor circuit that has been designed for optimum performance while processing a differential input signal. The clock signal alternatively switches the input between sample mode and hold mode (see Figure 29). When the input is switched to sample mode, the signal source must be capable of charging the sample capacitors and settling within 1/2 of a clock cycle.
Rev. 0 | Page 16 of 32
AD6642
Differential Input Configurations
Optimum performance is achieved when driving the AD6642 in a differential input configuration. For baseband applications, the AD8138, ADA4937-2, and ADA4938-2 differential drivers provide excellent performance and a flexible interface to the ADC. The output common-mode voltage of the ADA4938-2 is easily set with the VCMx pin of the AD6642 (see Figure 30), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal.
15pF 200 VIN 76.8 90 33 5pF 15 VIN- AVDD ADC 15 VIN+ VCM
08563-039
The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few megahertz (MHz). Excessive signal power can also cause core saturation, which leads to distortion. At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true SNR performance of the AD6642. For applications in which SNR is a key parameter, differential double balun coupling is the recommended input configuration (see Figure 32). In this configuration, the input is ac-coupled and the CML is provided to each input through a 33 resistor. These resistors compensate for losses in the input baluns to provide a 50 impedance to the driver. In the double balun and transformer configurations, the value of the input capacitors and resistors is dependent on the input frequency and source impedance and may need to be reduced or removed. Table 10 lists recommended values to set the RC network. At higher input frequencies, good performance can be achieved by using a ferrite bead in series with a resistor and removing the capacitors. However, these values are dependent on the input signal and should be used only as a starting guide. Table 10. Example RC Network
Frequency Range (MHz) 0 to 100 100 to 200 100 to 300
1
ADA4938-2
0.1F 120 200 15pF 33
Figure 30. Differential Input Configuration Using the ADA4938-2
For baseband applications where SNR is a key parameter, differential transformer coupling is the recommended input configuration. An example is shown in Figure 31. To bias the analog input, the VCM voltage can be connected to the center tap of the secondary winding of the transformer.
C2 R2 R1 2V p-p 49.9 C1 R1 0.1F R2 VIN- ADC VCM
08563-040
VIN+
R1 Series (Each) 33 10 10 1
C1 Differential 5 pF 5 pF Remove
R2 Series (Each) 15 10 66
C2 Shunt (Each) 15 pF 10 pF Remove
In this configuration, R1 is a ferrite bead with a value of 10 @ 100 MHz.
C2
Figure 31. Differential Transformer-Coupled Configuration
An alternative to using a transformer-coupled input at frequencies in the second Nyquist zone is to use the AD8352 differential driver (see Figure 33). For more information, see the AD8352 data sheet.
C2
0.1F 2V p-p PA S S P
0.1F 33 33 0.1F
R1
R2
VIN+ ADC
C1 R1 R2 VIN-
0.1F
VCM
08563-041
C2
Figure 32. Differential Double Balun Input Configuration
VCC 0.1F 0 16 1 2 CD RD RG 3 4 ANALOG INPUT 5 0.1F 0 14 0.1F 0.1F AD8352 10 0.1F 200 R 0.1F 0.1F 200 C VIN- ADC VCM
08563-042
ANALOG INPUT
8, 13 11
R
VIN+
Figure 33. Differential Input Configuration Using the AD8352
Rev. 0 | Page 17 of 32
AD6642
ANALOG INPUT XFMR 1:4 Z ETC4-1T-7 0.1F 0.1F 0.1F 0.1F 121 431nH INPUT Z = 50 121 33 3.0k AIN- 3.0pF ADC INTERNAL INPUT Z 33 0.1F
CML
Figure 34. 1:4 Transformer Passive Configuration
1000pF 180nH 220nH
1H VPOS
165 301 5.1pF 3.9pF 165
AD8376
1H 1nF
15pF CML 1nF 68nH 3.0k3.0pF
AD6642
1000pF
180nH 220nH
08563-115
NOTES 1. ALL INDUCTORS ARE COILCRAFT 0603CS COMPONENTS WITH THE EXCEPTION OF THE 1H CHOKE INDUCTORS (0603LS).
Figure 35. Active Front-End Configuration Using the AD8376
For the popular IF band of 140 MHz, Figure 34 shows an example of a 1:4 transformer passive configuration where a differential inductor is used to resonate with the internal input capacitance of the AD6642. This configuration realizes excellent noise and distortion performance. Figure 35 shows an example of an active front-end configuration using the AD8376 dual VGA. This configuration is recommended when signal gain is required.
Figure 37 and Figure 38 show two preferred methods for clocking the AD6642 (at clock rates up to 625 MHz). A low jitter clock source is converted from a single-ended signal to a differential signal using either an RF balun or an RF transformer. The RF balun configuration is recommended for clock frequencies between 125 MHz and 625 MHz, and the RF transformer configuration is recommended for clock frequencies from 10 MHz to 200 MHz. The back-to-back Schottky diodes across the transformer/balun secondary limit clock excursions into the AD6642 to approximately 0.8 V p-p differential. This limit helps to prevent the large voltage swings of the clock from feeding through to other portions of the AD6642 while preserving the fast rise and fall times of the signal that are critical to a low jitter performance.
ADT1-1WT, 1:1Z 0.1F XFMR 100 0.1F 0.1F SCHOTTKY DIODES: HSMS2822
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD6642 sample clock inputs, CLK+ and CLK-, should be clocked with a differential signal. The signal is typically ac-coupled into the CLK+ and CLK- pins via a transformer or capacitors. These pins are biased internally (see Figure 36) and require no external bias.
AVDD
1.2V CLK+ CLK-
0.1F CLOCK INPUT 50
08563-116
CLK+ ADC CLK-
2pF
2pF
08563-055
Figure 37. Transformer-Coupled Differential Clock (Up to 200 MHz)
Figure 36. Equivalent Clock Input Circuit
Clock Input Options
The AD6642 has a very flexible clock input structure. The clock input can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of the type of signal being used, clock source jitter is of the most concern (see the Jitter Considerations section).
CLOCK INPUT
1nF 50 1nF
0.1F CLK+ 0.1F SCHOTTKY DIODES: HSMS2822 ADC CLK-
08563-057
Figure 38. Balun-Coupled Differential Clock (Up to 625 MHz)
Rev. 0 | Page 18 of 32
08563-056
AD6642
If a low jitter clock source is not available, another option is to ac-couple a differential PECL signal to the sample clock input pins, as shown in Figure 39. The AD9510/AD9511/AD9512/ AD9513/AD9514/AD9515/AD9516 clock drivers offer excellent jitter performance.
0.1F 0.1F CLK+ AD951x PECL DRIVER 240 240 100 0.1F ADC CLK-
08563-058
VCC CLOCK INPUT 0.1F 50 1 1k 1k 0.1F
08563-061
AD951x CMOS DRIVER
OPTIONAL 0.1F 100
CLK+ ADC CLK-
150 RESISTOR IS OPTIONAL.
CLOCK INPUT
Figure 42. Single-Ended 3.3 V CMOS Input Clock (Up to 200 MHz)
CLOCK INPUT
0.1F 50k 50k
Input Clock Divider
The AD6642 contains an input clock divider with the ability to divide the input clock by integer values from 1 to 8. The AD6642 clock divider can be synchronized using the external SYNC input. Bit 1 of Register 0x3A enables the clock divider to be resynchronized on every SYNC signal. A valid SYNC causes the clock divider to reset to its initial state. This synchronization feature allows multiple parts to have their clock dividers aligned to guarantee simultaneous input sampling.
Figure 39. Differential PECL Sample Clock (Up to 625 MHz)
A third option is to ac-couple a differential LVDS signal to the sample clock input pins, as shown in Figure 40. The AD9510/ AD9511/AD9512/AD9513/AD9514/AD9515/AD9516 clock drivers offer excellent jitter performance.
0.1F 0.1F CLK+ AD951x LVDS DRIVER 100 0.1F ADC CLK-
08563-059
Clock Duty Cycle
CLOCK INPUT
CLOCK INPUT
0.1F 50k 50k
Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD6642 contains a duty cycle stabilizer (DCS) that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. This allows the user to provide a wide range of clock input duty cycles without affecting the performance of the AD6642. Noise and distortion performance are nearly flat for a wide range of duty cycles with the DCS enabled. Jitter in the rising edge of the input is still of paramount concern and is not easily reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates less than 40 MHz nominally. The loop has a time constant associated with it that must be considered in applications in which the clock rate can change dynamically. A wait time of 1.5 s to 5 s is required after a dynamic clock frequency increase or decrease before the DCS loop is relocked to the input signal. During the time period that the loop is not locked, the DCS loop is bypassed, and internal device timing is dependent on the duty cycle of the input clock signal.
Figure 40. Differential LVDS Sample Clock (Up to 625 MHz)
In some applications, it may be acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, the CLK+ pin should be driven directly from a CMOS gate, and the CLK- pin should be bypassed to ground with a 0.1 F capacitor in parallel with a 39 k resistor (see Figure 41).
VCC 0.1F CLOCK INPUT 501 1k 1k AD951x CMOS DRIVER OPTIONAL 0.1F 100 CLK+ ADC CLK- 0.1F
150
08563-060
39k
RESISTOR IS OPTIONAL.
Figure 41. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
CLK+ can be driven directly from a CMOS gate. Although the CLK+ input circuit supply is AVDD (1.8 V), this input is designed to withstand input voltages of up to 3.6 V, making the selection of the drive logic voltage very flexible (see Figure 42).
Rev. 0 | Page 19 of 32
AD6642
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR from the low frequency SNR (SNRLF) at a given input frequency (fIN) due to jitter (tJRMS) can be calculated by SNRHF = -10log[(2 x fIN x tJRMS)2 + 10(-SNRLF/10) ] In the equation, the rms aperture jitter represents the clock input jitter specification. IF undersampling applications are particularly sensitive to jitter, as illustrated in Figure 43.
80 0.05ps
1.5 1.4 1.3 1.2 1.1
TOTAL POWER (W)
0.30 IAVDD
0.25
1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
30 40 50 60 70 80 90 100 120 130 140 150 160 170 180 190 200 110
0.20
CURRENT (A)
08563-142
0.15 TOTAL POWER 0.10 IDRVDD 0.05
0 SAMPLING FREQUENCY (MSPS)
75
70
SNR (dBc)
0.20ps 65 0.50ps
Figure 44. Power and Current vs. Sampling Frequency
60
55
1.00ps 1.50ps 1 10 100 INPUT FREQUENCY (MHz) 1k
08563-053
50
By asserting PDWN (either through the SPI port or by asserting the PDWN pin high), the AD6642 is placed in power-down mode. In this state, the ADC typically dissipates 4.5 mW. During power-down, the output drivers are placed in a high impedance state. Asserting the PDWN pin low returns the AD6642 to its normal operating mode. Note that PDWN is referenced to the digital output driver supply (DRVDD) and should not exceed that supply voltage. Low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. Internal capacitors are discharged when entering power-down mode and must be recharged when returning to normal operation. As a result, wake-up time is related to the time spent in power-down mode; shorter power-down cycles result in proportionally shorter wake-up times. When using the SPI port interface, the user can place the ADC in power-down mode or standby mode. Standby mode allows the user to keep the internal reference circuitry powered when faster wake-up times are required. See the Memory Map Register Descriptions section for more details.
Figure 43. SNR vs. Input Frequency and Jitter
The clock input should be treated as an analog signal in cases in which aperture jitter may affect the dynamic range of the AD6642. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or another method), it should be retimed by the original clock at the last step. Refer to Application Note AN-501 and Application Note AN-756 for more information about jitter performance as it relates to ADCs (see www.analog.com).
POWER DISSIPATION AND STANDBY MODE
The power dissipated by the AD6642 is proportional to its clock rate (see Figure 44). The digital power dissipation does not vary significantly because it is determined primarily by the DRVDD supply and the bias current of the LVDS drivers. Reducing the capacitive load presented to the output drivers can minimize digital power consumption. The data in Figure 44 was taken using the same operating conditions as those used in the Typical Performance Characteristics section, with a 5 pF load on each output driver.
CHANNEL/CHIP SYNCHRONIZATION
The AD6642 has a SYNC input that offers the user flexible synchronization options for synchronizing the clock divider. The clock divider sync feature is useful for guaranteeing synchronized sample clocks across multiple ADCs. The SYNC input is internally synchronized to the sample clock; however, to ensure that there is no timing uncertainty between multiple parts, the SYNC input signal should be externally synchronized to the input clock signal, meeting the setup and hold times shown in Table 5. The SYNC input should be driven using a single-ended CMOS-type signal.
Rev. 0 | Page 20 of 32
AD6642
DIGITAL OUTPUTS
The AD6642 output drivers are configured to interface with LVDS outputs using a DRVDD supply voltage of 1.8 V. The output bits are DDR LVDS as shown in Figure 2. Applications that require the ADC to drive large capacitive loads or large fanouts may require external buffers or latches. As described in Application Note AN-877, Interfacing to High Speed ADCs via SPI, the data format can be selected for offset binary or twos complement when using the SPI control. The length of the output data lines and the loads placed on them should be minimized to reduce transients within the AD6642. These transients can degrade converter dynamic performance. The lowest typical conversion rate of the AD6642 is 40 MSPS. At clock rates below 40 MSPS, dynamic performance can degrade.
Data Clock Output (DCO)
The AD6642 provides a data clock output (DCO) signal intended for capturing the data in an external register. The output data for Channel A is valid on the rising edge of DCO; the output data for Channel B is valid on the falling edge of DCO. See Figure 2 for a graphical timing description.
TIMING
The AD6642 provides latched data with a pipeline delay of nine clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. Table 11. Output Data Format
Input (V) VIN+ - VIN- VIN+ - VIN- VIN+ - VIN- VIN+ - VIN- VIN+ - VIN- Condition (V) < -VREF - 0.5 LSB = -VREF =0 = +VREF - 1.0 LSB > +VREF - 0.5 LSB
Offset Binary Output Mode 0000 0000 0000 0000 0000 0000 0000 0000 1000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1111
Twos Complement Mode 1000 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 0111 1111 1111 1111 0111 1111 1111 1111
Rev. 0 | Page 21 of 32
AD6642 NOISE SHAPING REQUANTIZER (NSR)
The AD6642 features a noise shaping requantizer (NSR) to allow higher than 11-bit SNR to be maintained in a subset of the Nyquist band. The harmonic performance of the receiver is unaffected by the NSR feature. When enabled, the NSR contributes an additional 0.6 dB of loss to the input signal, such that a 0 dBFS input is reduced to -0.6 dBFS at the output pins. The NSR feature can be independently controlled per channel via the SPI or the MODE pin. Two different bandwidth modes are provided; the mode can be selected from the SPI port. In each of the two modes, the center frequency of the band can be tuned such that IFs can be placed anywhere in the Nyquist band.
0
NSR 22% BW MODE, TW = 28 SNR = 73.4dB (75dBFS) (IN-BAND) SFDR = 93dBc (IN-BAND)
fS = 184.32MSPS fIN = 140MHz @ -1.6dBFS
-20
AMPLITUDE (dBFS)
-40
-60
-80
-100
0
10
20
30
40
50
60
70
80
90
22% BW MODE (>40 MHZ @ 184.32 MSPS)
The first bandwidth mode offers excellent noise performance over 22% of the ADC sample rate (44% of the Nyquist band) and can be centered by setting the NSR mode bits in the NSR control register (Address 0x3C) to 000. In this mode, the useful frequency range can be set using the 6-bit tuning word in the NSR tuning register (Address 0x3E). There are 57 possible tuning words (TW); each step is 0.5% of the ADC sample rate. The following three equations describe the left band edge (f0), the channel center (fCENTER), and the right band edge (f1), respectively. f0 = fADC x .005 x TW fCENTER = f0 x 0.11 x fADC f1 = f0 x 0.22 x fADC Figure 45 to Figure 47 show the typical spectrum that can be expected from the AD6642 in the 22% BW mode for three different tuning words.
0 fS = 184.32MSPS fIN = 140MHz @ -1.6dBFS 0 10 20 30 0
FREQUENCY (MHz)
Figure 46. 22% BW Mode, Tuning Word = 28 (fS/4 Tuning)
fS = 184.32MSPS fIN = 140MHz @ -1.6dBFS NSR 22% BW MODE, TW = 41 SNR = 73.4dB (75dBFS) (IN-BAND) SFDR = 94dBc (IN-BAND)
-20
AMPLITUDE (dBFS)
-40
-60
-80
-100
40
50
60
70
80
90
FREQUENCY (MHz)
Figure 47. 22% BW Mode, Tuning Word = 41
33% BW MODE (>60 MHZ @ 184.32 MSPS)
The second bandwidth mode offers excellent noise performance over 33% of the ADC sample rate (66% of the Nyquist band) and can be centered by setting the NSR mode bits in the NSR control register (Address 0x3C) to 001. In this mode, the useful frequency range can be set using the 6-bit tuning word in the NSR tuning register (Address 0x3E). There are 34 possible tuning words (TW); each step is 0.5% of the ADC sample rate. The following three equations describe the left band edge (f0), the channel center (fCENTER), and the right band edge (f1), respectively. f0 = fADC x .005 x TW fCENTER = f0 x 0.165 x fADC f1 = f0 x 0.33 x fADC
-20
NSR 22% BW MODE, TW = 13 SNR = 73.4dB (75dBFS) (IN-BAND) SFDR = 92.6dBc (IN-BAND)
AMPLITUDE (dBFS)
-40
-60
-80
-100
0
10
20
30
40
50
60
70
80
90
FREQUENCY (MHz)
Figure 45. 22% BW Mode, Tuning Word = 13
08563-044
-120
Rev. 0 | Page 22 of 32
08563-046
-120
08563-045
-120
AD6642
Figure 48 to Figure 50 show the typical spectrum that can be expected from the AD6642 in the 33% BW mode for three different tuning words.
0
AMPLITUDE (dBFS)
NSR 33% BW MODE, TW = 5 SNR = 71dB (72.5dBFS) (IN-BAND) SFDR = 92.5dBc (IN-BAND)
0 fS = 184.32MSPS fIN = 140MHz @ -1.6dBFS
-20
NSR 33% BW MODE, TW = 27 SNR = 71dB (72.5dBFS) (IN-BAND) SFDR = 93dBc (IN-BAND)
fS = 184.32MSPS fIN = 140MHz @ -1.6dBFS
-40
-20
-60
AMPLITUDE (dBFS)
-40
-80
-60 -100 -80 0 10 20 30 40 50 60 70 80 90
08563-049
-120 -100
FREQUENCY (MHz)
Figure 50. 33% BW Mode, Tuning Word = 27
0 10 20 30 40 50 60 70 80 90
08563-047
-120
MODE PIN
The MODE pin input allows convenient control of the NSR feature. A logic low enables NSR mode and a logic high sets the receiver to straight 11-bit mode with NSR disabled. By default, the MODE pin is pulled high internally to disable the NSR. Each channel can be individually configured to ignore the MODE pin state by writing to Bit 4 of the NSR control register at Address 0x3C. Use of the NSR control register in conjunction with the MODE pin allows for very flexible control of the NSR feature on a per-channel basis.
FREQUENCY (MHz)
Figure 48. 33% BW Mode, Tuning Word = 5
0 fS = 184.32MSPS fIN = 140MHz @ -1.6dBFS NSR 33% BW MODE, TW = 17 SNR = 71.2dB (72.8dBFS) (IN-BAND) SFDR = 93.7dBc (IN-BAND)
-20
AMPLITUDE (dBFS)
-40
-60
-80
-100
0
10
20
30
40
50
60
70
80
90
FREQUENCY (MHz)
Figure 49. 33% BW Mode, Tuning Word = 17 (fS/4 Tuning)
08563-048
-120
Rev. 0 | Page 23 of 32
AD6642 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
The AD6642 includes built-in test features designed to verify the integrity of each channel and to facilitate board-level debugging. A BIST (built-in self-test) feature is included that verifies the integrity of the digital datapath of the AD6642. Various output test options are also provided to place predictable values on the outputs of the AD6642. The outputs are not disconnected during this test, so the PN sequence can be observed as it runs. The PN sequence can be continued from its last value or reset from the beginning, based on the value programmed in Register 0x0E, Bit 2. The BIST signature result varies based on the channel configuration.
OUTPUT TEST MODES
The output test options are shown in Table 13. When an output test mode is enabled, the analog section of the receiver is disconnected from the digital back-end blocks, and the test pattern is run through the output formatting block. Some of the test patterns are subject to output formatting. The seed value for the PN sequence tests can be forced if the PN reset bits are used to hold the generator in reset mode by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they require an encode clock. For more information, see Application Note AN-877, Interfacing to High Speed ADCs via SPI.
BUILT-IN SELF-TEST (BIST)
The BIST is a thorough test of the digital portion of the selected AD6642 signal path. When enabled, the test runs from an internal pseudorandom noise (PN) source through the digital datapath starting at the ADC block output. The BIST sequence runs for 512 cycles and stops. The BIST signature value for the selected channel is written to Register 0x24 and Register 0x25. If one channel is selected, its BIST signature is written to the two registers. If Channel A and Channel B are both selected, the results from Channel A are written to the BIST signature registers.
Rev. 0 | Page 24 of 32
AD6642 SERIAL PORT INTERFACE (SPI)
The AD6642 serial port interface (SPI) allows the user to configure the receiver for specific functions or operations through a structured internal register space. The SPI provides added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields, which are documented in the Memory Map section. For detailed operational information, see Application Note AN-877, Interfacing to High Speed ADCs via SPI. During an instruction phase, a 16-bit instruction is transmitted. The first bit of the first byte in a serial data transfer frame indicates whether a read command or a write command is issued. Data follows the instruction phase, and its length is determined by the W0 and W1 bits. All data is composed of 8-bit words. The instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. If the instruction is a read operation, the serial data input/output (SDIO) pin changes direction from an input to an output at the appropriate point in the serial frame. Data can be sent in MSB first mode or in LSB first mode. MSB first is the default mode on power-up and can be changed via the SPI port configuration register. For more information about this and other features, see Application Note AN-877, Interfacing to High Speed ADCs via SPI.
CONFIGURATION USING THE SPI
Three pins define the SPI of the AD6642: SCLK, SDIO, and CSB (see Table 12). SCLK (a serial clock) is used to synchronize the read and write data presented from and to the AD6642. SDIO (serial data input/output) is a bidirectional pin that allows data to be sent to and read from the internal memory map registers. CSB (chip select bar) is an active low control that enables or disables the read and write cycles. Table 12. Serial Port Interface Pins
Pin SCLK SDIO Function Serial clock. Serial shift clock input. SCLK is used to synchronize serial interface reads and writes. Serial data input/output. Bidirectional pin that serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. Chip select bar (active low). This control gates the read and write cycles.
HARDWARE INTERFACE
The pins described in Table 12 constitute the physical interface between the user programming device and the serial port of the AD6642. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during the write phase and as an output during readback. The SPI interface is flexible enough to be controlled by either FPGAs or microcontrollers. One method for SPI configuration is described in detail in Application Note AN-812, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit. The SPI port should not be active during periods when the full dynamic performance of the AD6642 is required. Because the SCLK signal, the CSB signal, and the SDIO signal are typically asynchronous to the ADC clock, noise from these signals can degrade AD6642 performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD6642 to prevent these signals from transitioning at the receiver inputs during critical sampling periods.
CSB
The falling edge of the CSB pin, in conjunction with the rising edge of the SCLK pin, determines the start of the framing. An example of the serial timing can be found in Figure 51 (for symbol definitions, see Table 5). CSB can be held low indefinitely, which permanently enables the device; this is called streaming. CSB can stall high between bytes to allow for additional external timing. When CSB is tied high, SPI functions are placed in high impedance mode.
tDS tS
CSB
tHIGH tDH tLOW
tCLK
tH
SCLK DON'T CARE
DON'T CARE
SDIO
DON'T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
DON'T CARE
Figure 51. Serial Port Interface Timing Diagram
Rev. 0 | Page 25 of 32
08563-073
AD6642 MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
Each row in the memory map register table has eight bit locations (see Table 13). The memory map is roughly divided into four sections: the chip configuration registers (Address 0x00 and Address 0x01); the channel index and transfer registers (Address 0x05 and Address 0xFF); the ADC function registers, including setup, control, and test (Address 0x08 to Address 0x25); and the digital feature control registers (Address 0x3A to Address 0x3E). The memory map register table (see Table 13) provides the default hexadecimal value for each hexadecimal address shown. The column with the heading (MSB) Bit 7 is the start of the default hexadecimal value given. Application Note AN-877, Interfacing to High Speed ADCs via SPI, documents the functions controlled by Register 0x00 to Register 0xFF. The remaining registers, Register 0x3A to Register 0x3E, are documented in the Memory Map Register Descriptions section.
Logic Levels
An explanation of logic level terminology follows: * * "Bit is set" is synonymous with "bit is set to Logic 1" or "writing Logic 1 for the bit." "Clear a bit" is synonymous with "bit is set to Logic 0" or "writing Logic 0 for the bit."
Transfer Register Map
Address 0x08 to Address 0x3E are shadowed. Writes to these addresses do not affect part operation until a transfer command is issued by writing 0x01 to Address 0xFF, setting the transfer bit. This allows these registers to be updated internally and simultaneously when the transfer bit is set. The transfer bit is autoclearing.
Channel-Specific Registers
Some channel setup functions, such as the NSR control function, can be programmed differently for each channel. In these cases, channel address locations are internally duplicated for each channel. These registers and bits are designated in Table 13 as local. Local registers and bits can be accessed by setting the appropriate channel bits in Register 0x05. If multiple channel bits are set, the subsequent write affects the registers of all selected channels. In a read cycle, only a single channel should be selected to read one of the registers. If multiple channels are selected during a SPI read cycle, the part returns the value for Channel A only. Registers and bits designated as global in Table 13 affect the entire part or the channel features for which there are no independent per-channel settings. The settings in Register 0x05 do not affect the global registers and bits.
Open Locations
All address and bit locations that are not included in Table 13 are not currently supported for this device. Unused bits of a valid address location should be written with 0s. Writing to these locations is required only when part of an address location is open (for example, Address 0x18). If the entire address location is open (for example, Address 0x13), this address location should not be written.
Default Values
After the AD6642 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table (see Table 13).
Rev. 0 | Page 26 of 32
AD6642
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 13 are not currently supported for this device. Table 13. Memory Map Registers
Addr. Register (MSB) (Hex) Name Bit 7 Chip Configuration Registers 0x00 SPI port Open configuration (global) Bit 6 LSB first Bit 5 Soft reset Bit 4 1 Bit 3 Bit 2 Soft reset Bit 1 LSB first (LSB) Bit 0 Open Default Value (Hex) 0x18 Comments Nibbles are mirrored so that LSB first or MSB first mode is set correctly, regardless of shift mode. To control this register, all channel index bits in Register 0x05 must be set. Read only.
1
0x01
Chip ID (global) Channel Index and Transfer Registers 0x05 Channel Open index
8-bit chip ID, Bits[7:0] AD6642 = 0x7A (default) Enable output port for Channel A and Channel B Open Open Open Open Channel B enable Channel A enable
0x7A
0xCF
0xFF
Transfer
Open
Open
Open
Open
Open
Open
Open
SW transfer 1 = on 0 = off (default)
0x00
Bits are set to determine which channel on the chip receives the next write command; applies to local registers. Synchronously transfers data from the master shift register to the slave. Determines generic modes of chip operation.
ADC Function Registers 0x08 Power modes Open
Open
0x0B
Clock divide (global)
Open
Open
Open Open External powerdown pin function (global) 0 = full powerdown 1= standby Clock divide phase 000 = 0 input clock cycles delayed 001 = 1 input clock cycle delayed 010 = 2 input clock cycles delayed
Open
Internal power-down mode (local) 00 = normal operation (default) 01 = full power-down 10 = standby
0x00
0x0C
Shuffle mode (local)
Open
Open
Open
Open
Open
Clock divide ratio 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 Open Shuffle mode enable 00 = shuffle disabled 01 = shuffle enabled
0x00
0x01
Enables or disables shuffle mode
Rev. 0 | Page 27 of 32
AD6642
Addr. (Hex) 0x0D Register Name Test mode (local) (MSB) Bit 7 Open Bit 6 Open Bit 2 Bit 1 Output test mode 000 = off (normal operation) 001 = midscale short 010 = positive FS 011 = negative FS 100 = alternating checkerboard 101 = PN sequence long 110 = PN sequence short 111 = 1/0 word toggle Open BIST Open Open Open BIST reset enable 0 = on 1 = on 1 = off 0 = off (default) (default) Offset adjustment in LSBs from +127 to -128 (twos complement format) 011111 = +31 LSB 011110 = +30 LSB 011101 = +29 LSB ... 000010 = +2 LSB 000001 = +1 LSB 000000 = 0 LSB ... 111111 = -1 LSB 111110 = -2 LSB 111101 = -3 LSB ... 100001 = -31 LSB 100000 = -32 LSB Output format (local) Open Output Open Output 00 = offset binary invert enable bar 01 = twos (local) (local) complement 1 = on 1 = off 0 = off 0 = on Open Open Output port LVDS drive current 0000 = 3.72 mA 0001 = 3.5 mA (default) 0010 = 3.3 mA 0011 = 2.96 mA 0100 = 2.82 mA 0101 = 2.57 mA 0110 = 2.27 mA 0111 = 2.0 mA 1000 = 2.0 mA Open Open Open Open Open Open Bit 5 Reset long PN generator 0 = on 1 = off (default) Bit 4 Reset short PN generator 0 = on 1 = off (default) Bit 3 Open (LSB) Bit 0 Default Value (Hex) 0x00 Comments When set, the test data is placed on the output pins in place of normal data.
0x0E
BIST enable (local)
Open
Open
0x00
0x10
Offset adjust (local)
Open
Open
0x00
When Bit 0 is set, the built-in selftest function is initiated. Device offset trim.
0x14
Output mode (local)
Open
Open
0x00
0x15
Output adjust (local)
Open
Open
0x01
Configures the outputs and the format of the data. Output current adjustments.
0x16
Clock phase control (local) DCO output delay (global)
0x17
Invert DCO clock 0 = off 1 = on DCO delay enable 0 = off 1 = on
Open
0x00
Open
Open
0x18
VREF select (global)
Open
Open
Open
Output port DCO clock delay 00000 = 100 ps additional delay on the DCO pin 00001 = 200 ps additional delay on the DCO pin 00010 = 300 ps additional delay on the DCO pin ... 11101 = 3.0 ns additional delay on the DCO pin 11110 = 3.1 ns additional delay on the DCO pin 11111 = 3.2 ns additional delay on the DCO pin Internal VREF full-scale adjustment Main reference full-scale VREF adjustment 01111: internal 2.087 V p-p ... 00001: internal 1.772 V p-p 00000: internal 1.75 V p-p ... 11111: internal 1.727 V p-p ... 10000: internal 1.383 V p-p
Rev. 0 | Page 28 of 32
0x00
When Bit 7 is set, clock polarity is reversed. Enable DCO delay and set the delay time.
0x00
Select adjustments for VREF.
AD6642
Addr. (Hex) 0x24 Register (MSB) Name Bit 7 BIST signature LSB (local) 0x25 BIST signature MSB (local) Digital Feature Control Registers 0x3A Sync control Open (global) Bit 6 Bit 5 Bit 4 Bit 3 BIST Signature[7:0] BIST Signature[15:8] Bit 2 Bit 1 (LSB) Bit 0 Default Value (Hex) 0x00 0x00 Comments Read only. Read only.
Open
Open
Open
Open
Open
Clock divider sync enable 0 = off 1 = on
Master sync enable 0 = off 1 = on NSR enable 0 = off 1 = on (used only if Bit 4 = 1; otherwise ignored)
0x00
Control register to synchronize the clock divider. Noise shaping requantizer (NSR) controls.
0x3C
NSR control (local)
Open
Open
Open
MODE pin disable 0 = MODE pin used 1 = MODE pin disabled
NSR mode 000 = 22% BW mode 001 = 33% BW mode
0x00
0x3E
NSR tuning word (local)
Open
Open
NSR tuning word See the Noise Shaping Requantizer (NSR) section. Equations for the tuning word are dependent on the NSR mode.
0x1C
NSR frequency tuning word.
MEMORY MAP REGISTER DESCRIPTIONS
For additional information about functions controlled in Register 0x00 to Register 0xFF, see Application Note AN-877, Interfacing to High Speed ADCs via SPI.
Bits[3:1]-- NSR Mode
Bits[3:1] determine the bandwidth mode of the NSR. When Bits[3:1] are set to 000, the NSR is configured for a 22% BW mode that provides enhanced SNR performance over 22% of the sample rate. When Bits[3:1] are set to 001, the NSR is configured for a 33% BW mode that provides enhanced SNR performance over 33% of the sample rate.
Sync Control (Register 0x3A) Bits[7:2]--Reserved Bit 1--Clock Divider Sync Enable
Bit 1 gates the sync pulse to the clock divider. The sync signal is enabled when Bit 1 is high and Bit 0 is high. This is continuous sync mode.
Bit 0--NSR Enable
The NSR is enabled when Bit 0 is high and disabled when Bit 0 is low. Bit 0 is ignored unless the MODE pin disable bit (Bit 4) is set.
Bit 0--Master Sync Enable
Bit 0 must be high to enable any of the sync functions. If the sync capability is not used, this bit should remain low to conserve power.
NSR Tuning Word (Register 0x3E) Bits[7:6]--Reserved Bits[5:0]-- NSR Tuning Word
The NSR tuning word sets the band edges of the NSR band. In 22% BW mode, there are 57 possible tuning words; in 33% BW mode, there are 34 possible tuning words. For either mode, each step represents 0.5% of the ADC sample rate. For the equations used to calculate the tuning word based on the BW mode of operation, see the Noise Shaping Requantizer (NSR) section.
NSR Control (Register 0x3C) Bits[7:5]--Reserved Bit 4--MODE Pin Disable
Bit 4 specifies whether the selected channels will be controlled by the MODE pin. Local registers act on the channels that are selected by the channel index register (Address 0x05).
Rev. 0 | Page 29 of 32
AD6642 APPLICATIONS INFORMATION
DESIGN GUIDELINES
Before starting the design and layout of the AD6642 as a system, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins.
VCMx Pins
The VCMx pins are provided to set the common-mode level of the analog inputs. The VCMx pins should be decoupled to ground with a 0.1 F capacitor, as shown in Figure 31.
SPI Port
The SPI port should not be active during periods when the full dynamic performance of the AD6642 is required. Because the SCLK signal, the CSB signal, and the SDIO signal are typically asynchronous to the ADC clock, noise from these signals can degrade AD6642 performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD6642 to prevent these signals from transitioning at the receiver inputs during critical sampling periods.
Power and Ground Recommendations
When connecting power to the AD6642, it is recommended that two separate 1.8 V supplies be used. Use one supply for analog (AVDD); use a separate supply for the digital outputs (DRVDD). The AVDD and DRVDD supplies should be isolated with separate decoupling capacitors. Several different decoupling capacitors can be used to cover both high and low frequencies. These capacitors should be located close to the point of entry at the PCB level and close to the pins of the part, with minimal trace length. A single PCB ground plane should be sufficient when using the AD6642. With proper decoupling and smart partitioning of the PCB analog, digital, and clock sections, optimum performance is easily achieved.
Rev. 0 | Page 30 of 32
AD6642 OUTLINE DIMENSIONS
10.10 10.00 9.90 BALL A1 INDICATOR 8.80 BSC SQ A1 CORNER INDEX AREA
9 7 3 1 5 12 11 10 8 6 4 2 A B C D E F G H J K L M
TOP VIEW
0.80 BSC DETAIL A 1.40 MAX
BOTTOM VIEW
DETAIL A
0.43 MAX 0.25 MIN 0.55 0.50 0.45 BALL DIAMETER COMPLIANT WITH JEDEC STANDARDS MO-205-AC. SEATING PLANE
1.00 0.85
COPLANARITY 0.12 MAX
Figure 52. 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-144-1) Dimensions shown in millimeters
ORDERING GUIDE
Model AD6642BBCZ 1 AD6642BBCZRL1 AD6642EBZ1
1
Temperature Range -40C to +85C -40C to +85C
Package Description 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] Evaluation Board
012006-0
Package Option BC-144-1 BC-144-1
Z = RoHS Compliant Part.
Rev. 0 | Page 31 of 32
AD6642 NOTES
(c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08563-0-10/09(0)
Rev. 0 | Page 32 of 32

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